For portable communication devices, such as radiotelephones, it is desirable to minimize the size of the radiotelephone (for portability and ease of handling) and to reduce power consumption. One way to reduce size and power consumption is through the use of bit-serial digital processing, wherein parallel arithmetic is transformed to serial arithmetic. The use of bit-serial processing reduces the gate count, silicon area, and current drain of integrated circuits when compared to parallel-formatted digital circuits. Bit-serial processing is generally accomplished through the use of three basic building blocks: a bit-serial adder, a bit-serial scaler, and a bit-serial delay element.
A conventional parallel adder has two parallel inputs and an output. For example, a conventional sixteen-bit parallel adder has two sixteen-bit parallel inputs and a sixteen-bit output, and it may be built with sixteen full adders. In contrast to a conventional parallel adder, a bit-serial adder consists of two one-bit inputs and a one-bit output. To achieve a dynamic range equivalent to that of a parallel adder, the clock rate of the bit-serial adder must be increased by a factor corresponding to the number of bits in the digital word. The following equation can be used to characterize the required increased clock rate for a bit-serial adder: EQU f.sub.bit =B*f.sub.sample
where f.sub.bit is the bit-serial adder clock rate, B is the number of bits in the digital word, and f.sub.sample is the digital word sampling rate. Each bit in a word, from the least significant bit (LSB) to the most significant bit (MSB), appears on the serial bus for one bit time period (1/f.sub.bit).
Bit-serial scaling is a form of digital multiplication wherein a digital word is scaled by a factor of 2.sup.-N. Bit-serial scaling is achieved by first producing versions of a digital word wherein the bits are shifted by N bits. The bit-shifted versions of the input word are summed to produce the digital word multiplied by a selected coefficient.
Bit-serial delays are generally implemented using a shift register. The shift register holds a bit for a predetermined number of bit time periods using flip-flops.
In many systems there are digital signals that operate at different sampling rates. In order to perform the necessary digital arithmetic, the sampling rates of all of the signals must be identical. Therefore, it is often necessary to increase the sampling rate of a digital signal by an integer factor M&gt;1. This is commonly referred to as interpolation.
The sampling rate increase may also be needed to achieve a finer resolution of received digital signals. This finer resolution is necessary, for example, to obtain a better frequency estimate of an incoming received digital signal. The zero-crossings of the signal can be used for the frequency estimation, and interpolation provides a more accurate estimation of the zero-crossings.
One approach used to achieve interpolation is by linearly interpolating (M-1) values between samples of the digital signal. For example, consider a sampling rate increase factor of M=4. If two successive samples, at the pre-interpolated sampling rate, are x(n)=1 and x(n+1)=5, then a linear interpolation would result in the following sequence: y={1,2,3,4,5}. One method to accomplish this mathematical computation would be a direct, brute-force mathematical computation through the use of a DSP.
Another approach to sampling rate increase is through the use of "zero-stuff" interpolation. Zero-stuff interpolating involves inserting (M-1) "zeroes" between existing data values of the input sequence x. Further processing of the zero-stuffed signal may be required, depending upon system requirements.
If further processing is required, the zero-stuffed sequence is then generally filtered. In addition, it is sometimes necessary to produce a sliced output representation of the zero-stuffed, interpolated signal. For example, if the frequency or phase of the interpolated signal is all that is desired, the zero crossings may be sufficient to provide this information.
A linear interpolator with a sliced output involves looking at a sign bit of the interpolated signal and then outputting a value depending upon the sign bit. For example, if successive samples, at the interpolated sampling rate are x(n)=-0.25 and x(n+1)=0.15, then a linear interpolation would result in the following sequence: y={-0.25, -0.15, -0.05, 0.05, 0.15}. If the digital system is defined such that asserted high corresponds to a negative number in the sequence and an asserted low corresponds to a positive number in the sequence, then the sliced output would be Y.sub.sliced =11100.
Filtering and slicing can be achieved through the use of a Finite Impulse Response (FIR) filter. However, for portable applications, such as portable communication devices, the direct implementation of an FIR filter can be hardware intensive and would thus consume too much space and power. The added space will thus increase the size of the portable communication device and the additional power required would reduce battery life.
Accordingly, when a system is based on a bit-serial architecture and an interpolated signal with a sliced output is desired, there is a need for a bit-serial architecture that does not require a complete FIR filter implementation.